Multiprocessor Emulation with Rpm: Early Experience

Field-Programmable Gate Arrays is an emerging technology which promises easy hardware reconfigurability by software at low cost. Entire systems can be built in which some parts are easily programmable. Such systems are flexible hardware platforms or emulators, which are then tailored to implement various architectures. The performance of these architectures can be compared on the same hardware substrate. Besides having a large speedup advantage over software simulation, the emulator is a detailed hardware implementation of the architecture --including I/O-on which complex software systems can be run without code instrumentation and it is a more convincing proof of concept. On the other hand it is much more cost-effective than a full-fledged prototype. We have built a multiprocessor emulator called RPM --Rapid Prototyping engine for Multiprocessor systems. RPM can emulate various configurations of shared-memory and message-passing systems. The bandwidth and latency of various components can be easily modified to match various processor, memory and interconnect technologies. In this paper, we present the modeling methodology, the performance collection mechanism, the calibration of the emulator as well as our first results obtained for the emulator of a cachecoherent non uniform memory access multiprocessor (CC-NUMA).